完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Huang, Yu-Ching | en_US |
dc.contributor.author | Ker, Ming-Dou | en_US |
dc.date.accessioned | 2014-12-08T15:30:41Z | - |
dc.date.available | 2014-12-08T15:30:41Z | - |
dc.date.issued | 2013-05-01 | en_US |
dc.identifier.issn | 0741-3106 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/LED.2013.2252456 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/21909 | - |
dc.description.abstract | Based on good electrostatic discharge (ESD) robustness, silicon-controlled rectifier (SCR) device is used for on-chip ESD protection. The major concern of SCR is the latch-up issue, because of its low holding voltage. Previous papers tried to design latchup-immune SCR devices; however, those devices would cause lower ESD robustness. In this letter, a new latchup-immune and robust SCR device for ESD protection is proposed and verified in a 0.25-mu m 5-V CMOS process. Through inserting one additional parasitic bipolar junction transistor into SCR device structure, this new proposed SCR can increase the holding voltage without causing degradation on its ESD robustness. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Electrostatic discharges (ESD) | en_US |
dc.subject | latchup | en_US |
dc.subject | silicon-controlled rectifier (SCR) | en_US |
dc.title | A Latchup-Immune and Robust SCR Device for ESD Protection in 0.25-mu m 5-V CMOS Process | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/LED.2013.2252456 | en_US |
dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
dc.citation.volume | 34 | en_US |
dc.citation.issue | 5 | en_US |
dc.citation.spage | 674 | en_US |
dc.citation.epage | 676 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000318433400034 | - |
dc.citation.woscount | 3 | - |
顯示於類別: | 期刊論文 |