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dc.contributor.authorWANG, THen_US
dc.contributor.authorHUANG, CMen_US
dc.contributor.authorCHANG, TEen_US
dc.contributor.authorCHOU, JWen_US
dc.contributor.authorCHANG, CYen_US
dc.date.accessioned2014-12-08T15:03:40Z-
dc.date.available2014-12-08T15:03:40Z-
dc.date.issued1994-12-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/16.337468en_US
dc.identifier.urihttp://hdl.handle.net/11536/2192-
dc.description.abstractAn interface trap assisted tunneling mechanism which includes hole tunneling from interface traps to the valence band and electron tunneling from interface traps to the conduction band is presented to model the drain leakage current in a 0.5 mu m LATID N-MOSFET. In experiment, the interface traps were generated by hot carrier stress, The increased drain leakage current due to the band-trap-band tunneling can be adequately described by an analytical expression of Delta I-d = A exp(-Bit/F) with a value of B-it of 13 MV/cm, which is much lower than that (36 MV/cm) of direct band-to-band tunneling.en_US
dc.language.isoen_USen_US
dc.titleINTERFACE-TRAP EFFECT ON GATE INDUCED DRAIN LEAKAGE CURRENT IN SUBMICRON N-MOSFETSen_US
dc.typeNoteen_US
dc.identifier.doi10.1109/16.337468en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume41en_US
dc.citation.issue12en_US
dc.citation.spage2475en_US
dc.citation.epage2477en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1994PW50100037-
dc.citation.woscount8-
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