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dc.contributor.authorPan, Tung-Mingen_US
dc.contributor.authorYen, Li-Chenen_US
dc.contributor.authorHuang, Sheng-Haoen_US
dc.contributor.authorLo, Chieh-Tingen_US
dc.contributor.authorChao, Tien-Shengen_US
dc.date.accessioned2014-12-08T15:31:14Z-
dc.date.available2014-12-08T15:31:14Z-
dc.date.issued2013-07-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2013.2261511en_US
dc.identifier.urihttp://hdl.handle.net/11536/22247-
dc.description.abstractIn this paper, we have successfully fabricated low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) nonvolatile memory devices employing high-kappa Eu2O3 and Y2O3 films as the charge trapping layer. The LTPS-TFT memory device uses band-to-band tunneling-induced hot hole injection and gate Fowler-Nordheim injection as the program and erase methods, respectively. Compared with the Y2O3 film, the LTPS-TFT memory device using an Eu2O3 charge-trapping layer exhibited a lower subthreshold swing and a larger memory window, a smaller charge loss, and a better endurance performance, presumably because of the higher charge-trapping efficiency of the Eu2O3 film.en_US
dc.language.isoen_USen_US
dc.subjectCharge-trapping layeren_US
dc.subjectEu2O3en_US
dc.subjectlow-temperature polycrystalline silicon thin-film transistor (LTPS-TFT)en_US
dc.subjectY2O3en_US
dc.titleHigh-kappa Eu2O3 and Y2O3 Poly-Si Thin-Film Transistor Nonvolatile Memory Devicesen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2013.2261511en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume60en_US
dc.citation.issue7en_US
dc.citation.spage2251en_US
dc.citation.epage2255en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.identifier.wosnumberWOS:000320870000023-
dc.citation.woscount1-
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