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dc.contributor.authorGuo, Jyh-Chyurnen_US
dc.contributor.authorLin, Yi-Minen_US
dc.contributor.authorTsai, Yi-Hsiuen_US
dc.date.accessioned2014-12-08T15:03:41Z-
dc.date.available2014-12-08T15:03:41Z-
dc.date.issued2008en_US
dc.identifier.isbn978-2-8748-7007-1en_US
dc.identifier.urihttp://hdl.handle.net/11536/2229-
dc.identifier.urihttp://dx.doi.org/10.1109/EMICC.2008.4772311en_US
dc.description.abstractRF noise shielding methods with different coverage areas (Pad and TML shielding) were implemented in two port test structures adopting 100-nm MOSFETs. Noise measurement reveals an effective suppression of NF(min) but increase of NF(50), simultaneously from the shielding methods. The suppression of NF(min) is contributed from the reduction of Re(Y(opt)) while the noise resistance R(n) is kept nearly the same. A lossy substrate model developed in our original work for a standard structure without shielding can be easily extended based on the layout and topology of the shielding schemes to predict the noise shielding effect and explain the mechanisms. The extended lossy substrate model indicates that the elimination of substrate loss represented by substrate RLC networks is the major mechanism contributing the reduction of NF(min). However, the increase of parasitic capacitance generated from the shielding structures is responsible for the degradation of f(T) and NF(50). The results provide an important insight and guideline for low noise RF circuit design.en_US
dc.language.isoen_USen_US
dc.titleRF Noise Shielding Method and Modelling for Nanoscale MOSFETen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/EMICC.2008.4772311en_US
dc.identifier.journal2008 EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC)en_US
dc.citation.spage390en_US
dc.citation.epage393en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000268721400099-
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