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dc.contributor.authorChen, Hung-Binen_US
dc.contributor.authorChang, Chun-Yenen_US
dc.contributor.authorLu, Nan-Hengen_US
dc.contributor.authorWu, Jia-Jiunen_US
dc.contributor.authorHan, Ming-Hungen_US
dc.contributor.authorCheng, Ya-Chien_US
dc.contributor.authorWu, Yung-Chunen_US
dc.date.accessioned2014-12-08T15:32:05Z-
dc.date.available2014-12-08T15:32:05Z-
dc.date.issued2013-07-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2013.2262018en_US
dc.identifier.urihttp://hdl.handle.net/11536/22604-
dc.description.abstractThis letter demonstrates for the first time junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with ultrathin channels (2 nm). The subthreshold swing is 61 mV/decade and the ON/OFF current ratio is close to 10(8) because of the excellent gate controllability and ultrathin channel. The JL-GAA TFTs have a low drain-induced barrier lowering value of 6 mV/V, indicating greater suppression of the short-channel effect than in JL-planar TFTs. The cumulative distribution of electrical parameters in JL-GAA is small. Therefore, the proposed JL-GAA TFTs of excellent device characteristics along with simple fabrication are highly promising for future system-on-panel and system-on-chip applications.en_US
dc.language.isoen_USen_US
dc.subjectGate-all-around (GAA)en_US
dc.subjectjunctionless (JL)en_US
dc.subjectthin-film transistoren_US
dc.subjectultrathin channelen_US
dc.titleCharacteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channelen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2013.2262018en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume34en_US
dc.citation.issue7en_US
dc.citation.spage897en_US
dc.citation.epage899en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000323685700025-
dc.citation.woscount4-
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