標題: | Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation |
作者: | Lin, Yi-Min Chang, Hsie-Chia Lee, Chen-Yi 電機工程學系 Department of Electrical and Computer Engineering |
關鍵字: | Bose-Chaudhuri-Hochquenghem (BCH) codes;error-correction coding;soft decoding |
公開日期: | 1-Nov-2013 |
摘要: | Compared with traditonal hard Bose-Chaudhuri-Hochquenghem (BCH) decoders, soft BCH decoders provide better error-correcting performance but much higher hardware complexity. In this brief, an improved soft BCH decoding algorithm is presented to achieve both competitive hardware complexity and better error-correcting performance by dealing with least reliable bits and compensating one extra error outside the least reliable set. For BCH (255, 239; 2) and (255, 231; 3) codes, our proposed soft BCH decoders can achieve up to 0.75-dB coding gain with one extra error compensation and 5% less complexity than the traditional hard BCH decoders. |
URI: | http://dx.doi.org/10.1109/TVLSI.2012.2227847 http://hdl.handle.net/11536/22675 |
ISSN: | 1063-8210 |
DOI: | 10.1109/TVLSI.2012.2227847 |
期刊: | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS |
Volume: | 21 |
Issue: | 11 |
起始頁: | 2160 |
結束頁: | 2164 |
Appears in Collections: | Articles |
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