標題: Design and Optimization of 6T SRAM using Vertically Stacked Nanowire MOSFETs
作者: Tsai, Ming-Fu
Fan, Ming-Long
Pao, Chia-Hao
Chen, Yin-Nien
Hu, Vita Pi-Ho
Su, Pin
Chuang, Ching-Te
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2013
摘要: This paper discusses the design and optimization of 6T SRAM cell using multiple stacked NanoWire (NW) MOSFETs. The results suggest that RSNM reaches the maximum when Pull-Up (PU) and Pull-Down (PD) transistors are stacked in equivalent number. Up to 40% and 91% improvement in RSNM are achieved at the cost of 7.5% and 5.9% degradation in WSNM using Floating-Power Write-assist compared with the case without stacking at V-DD = 0.3V and 1V, respectively. For robust design in subthreshold SRAM, raising V-trip by stacking PU transistors is more efficient than reducing Read disturb by stacking PD transistors under the premise of using quantized number of stacked NW. Moreover, we show that the stacked NW MOSFETs suppress the impact of Line-Edge Roughness (LER) variation and mitigate the variability in SRAM.
URI: http://hdl.handle.net/11536/22860
ISBN: 978-1-4673-3082-4
ISSN: 1524-766X
期刊: 2013 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA)
Appears in Collections:Conferences Paper