Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lin, Chen-Wei | en_US |
dc.contributor.author | Chen, Hung-Hsin | en_US |
dc.contributor.author | Yang, Hao-Yu | en_US |
dc.contributor.author | Chao, Mango C-T | en_US |
dc.contributor.author | Huang, Rei-Fu | en_US |
dc.date.accessioned | 2014-12-08T15:32:45Z | - |
dc.date.available | 2014-12-08T15:32:45Z | - |
dc.date.issued | 2010 | en_US |
dc.identifier.isbn | 978-1-4244-7205-5 | en_US |
dc.identifier.issn | 1089-3539 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/22890 | - |
dc.description.abstract | Due to the increasing demand of an extra-low-power system, a great amount of research effort has been spent in the past to develop an effective and economic subthreshold-SRAM design. However, the test methods regarding those newly developed subthreshold-SRAM designs have not yet been fully discussed. In this paper, we first categorize the subthreshold-SRAM designs into three types, study the faulty behavior of different open defects for each type of designs, and then identify the faults which may or may not be covered by a traditional SRAM test method. For those hard-to-detect faults, we will further discuss the corresponding test method according to different each type of subthreshold-SRAM designs. At last, a discussion about the temperature at test will also be provided. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Fault Models and Test Methods for Subthreshold SRAMs | en_US |
dc.type | Article | en_US |
dc.identifier.journal | INTERNATIONAL TEST CONFERENCE 2010 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000287978200047 | - |
Appears in Collections: | Conferences Paper |