Memory device application of wide-channel in-plane gate transistors with type-II GaAsSb-capped InAs quantum dots

doi:10.1063/1.4824067

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DC 欄位	值	語言
dc.contributor.author	Liao, Yu-An	en_US
dc.contributor.author	Chao, Yi-Kai	en_US
dc.contributor.author	Chang, Shu-Wei	en_US
dc.contributor.author	Chang, Wen-Hao	en_US
dc.contributor.author	Chyi, Jen-Inn	en_US
dc.contributor.author	Lin, Shih-Yen	en_US
dc.date.accessioned	2014-12-08T15:33:04Z	-
dc.date.available	2014-12-08T15:33:04Z	-
dc.date.issued	2013-09-30	en_US
dc.identifier.issn	0003-6951	en_US
dc.identifier.uri	http://dx.doi.org/10.1063/1.4824067	en_US
dc.identifier.uri	http://hdl.handle.net/11536/23019	-
dc.description.abstract	We demonstrate room-temperature electron charging/discharging phenomena of InAs quantum dots using wide-channel in-plane gate transistors. The device based on type-II GaAsSb-capped InAs quantum dots exhibits both the longer charging and discharging times than those of the type-I counterpart with GaAs capping layers. The slow charge relaxation of GaAsSb-capped InAs quantum dots and simple architecture of in-plane gate transistors reveal the potential of this device architecture for practical memory applications. (C) 2013 AIP Publishing LLC.	en_US
dc.language.iso	en_US	en_US
dc.title	Memory device application of wide-channel in-plane gate transistors with type-II GaAsSb-capped InAs quantum dots	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1063/1.4824067	en_US
dc.identifier.journal	APPLIED PHYSICS LETTERS	en_US
dc.citation.volume	103	en_US
dc.citation.issue	14	en_US
dc.citation.epage		en_US
dc.contributor.department	電子物理學系	zh_TW
dc.contributor.department	光電工程學系	zh_TW
dc.contributor.department	Department of Electrophysics	en_US
dc.contributor.department	Department of Photonics	en_US
dc.identifier.wosnumber	WOS:000325488500117	-
dc.citation.woscount	1	-
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