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dc.contributor.authorLiu, Wen-Haoen_US
dc.contributor.authorKoh, Cheng-Koken_US
dc.contributor.authorLi, Yih-Langen_US
dc.description.abstractRoutability has become a critical issue in VLSI design flow. To avoid producing an unroutable design, many placers [47] invoke global routers to get a congestion map and then move cells to reduce congestion based on this map. However, as cells move, the accuracy of the congestion map degrades, thereby affecting the effectiveness of the placer in minimizing congestions. Moreover, most global routers [8-13] ignore local congestion. If placers are guided by these routers, it may produce hard-to-route placement solutions in terms of detailed routing. This work develops a routability optimizer, called Ropt, to reduce both global and local routing congestion levels of a given placement. Based on a local-routability-aware routing model, Ropt builds a global routing instance to obtain global and local congestion information for guiding global re-placement. In addition, this work presents a new legalization scheme to preserve the global routing instance after legalization. Finally, local detailed placement further minimizes the local congestion and wirelength. For the evaluation of Ropt, we use an academic global router and a commercial router to obtain both global and detailed routing results, respectively. Experimental results reveal that Ropt can improve the routing quality (in terms of congestion, wirelength, and violation) and routing runtime of a given placement solution.en_US
dc.subjectglobal routingen_US
dc.subjectdetailed routingen_US
dc.subjectroutability optimizationen_US
dc.titleOptimization of Placement Solutions for Routabilityen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2013 50TH ACM / EDAC / IEEE DESIGN AUTOMATION CONFERENCE (DAC)en_US
dc.contributor.departmentDepartment of Computer Scienceen_US
Appears in Collections:Conferences Paper