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dc.contributor.authorChen, Shing-Yuen_US
dc.contributor.authorHsiao, Ming-Yien_US
dc.contributor.authorJone, Wen-Benen_US
dc.contributor.authorChen, Tien-Fuen_US
dc.date.accessioned2014-12-08T15:33:12Z-
dc.date.available2014-12-08T15:33:12Z-
dc.date.issued2013en_US
dc.identifier.isbn978-1-4673-4436-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/23090-
dc.description.abstractIn today's modern system-on-chips (SoCs), there are several intellectual properties (IPs) on the system to provide different functionality. However, the more complex communications on SoCs are, the harder the programmer could discover all errors before first silicon during verification. Therefore, we provide a reconfigurable unit for recording the transactions between IPs and adopt logical vector clock [1] as timestamp of each trace. The programmable trigger unit (PTU) in debugging node (DN) could be configured by the validator to cache their interest sequences of transaction. Because the traces of transactions would have their own timestamp, during the post-silicon validation, we could reproduce the errors in faulty transactions between IPs and get more information for bypassing or fixing the problems. Furthermore, due to several entries of traces, which would shrink observation window very quickly, we also implement a compressor to compress traces before we store them into trace buffer. Finally, our experiments demonstrate that the proposed debugging architecture is capable of recording the critical transactions, and by the proposed reconfigurable debugging unit the debugging execution time can be reduced more than 80%.en_US
dc.language.isoen_USen_US
dc.titleA Configurable Bus-Tracer for Error Reproduction in Post-Silicon Validationen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT)en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000326882100021-
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