Analysis and Solution to Overcome EOS Failure Induced by Latchup Test in A High-Voltage Integrated Circuits

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Tsai, Hui-Wen	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.author	Liu, Yi-Sheng	en_US
dc.contributor.author	Chuang, Ming-Nan	en_US
dc.date.accessioned	2014-12-08T15:33:13Z	-
dc.date.available	2014-12-08T15:33:13Z	-
dc.date.issued	2013	en_US
dc.identifier.isbn	978-1-4673-4436-4	en_US
dc.identifier.uri	http://hdl.handle.net/11536/23097	-
dc.description.abstract	Proper layout and additional circuit solution have been proposed to solve the practical EOS failure induced by latchup test in an industry case of high-voltage integrated circuits (IC). The modified design has been implemented in 0.6-um 40-V BCD (Bipolar-CMOS-DMOS) process to successfully pass the 500-mA negative trigger current test. By eliminating overstress damages as happened in the prior work with only guard ring protection, the proposed solution can be adopted to implement high-voltage-applicable IC products which meet the requirement of industry applications with sufficient latchup immunity.	en_US
dc.language.iso	en_US	en_US
dc.subject	Latchup	en_US
dc.subject	electrical overstress (EOS)	en_US
dc.subject	high-voltage IC	en_US
dc.subject	regulator	en_US
dc.title	Analysis and Solution to Overcome EOS Failure Induced by Latchup Test in A High-Voltage Integrated Circuits	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT)	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000326882100004	-
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