完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, Chun-Yi | en_US |
dc.contributor.author | Rao, Pei-Zong | en_US |
dc.contributor.author | Chiu, Hsen-Hung | en_US |
dc.contributor.author | Chung, Shyh-Jong | en_US |
dc.date.accessioned | 2014-12-08T15:33:15Z | - |
dc.date.available | 2014-12-08T15:33:15Z | - |
dc.date.issued | 2012 | en_US |
dc.identifier.isbn | 978-1-934142-20-2 | en_US |
dc.identifier.issn | 1559-9450 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/23142 | - |
dc.description.abstract | In this work, a 7.92 GHz ultra-low-voltage LC-tank voltage controlled oscillator (VCO) is introduced. The proposed LC-tank VCO adopts a NMOS cross-coupled topology and additional parallel capacitors for low voltage operation and phase noise reduction. The measured phase noise at 600 KHz frequency offset is -98 dBc/Hz and at 1 MHz offset is -108 dBc/Hz, respectively. The proposed VCO achieves a figure-of-merit (FOM) value of -187 dBc/Hz, drawing 0.87 mW from a 0.62V supply. The proposed circuit topology is designed for ultra wide-band (UWB) applications and implemented in TSMC 0.18 mu M CMOS technology. | en_US |
dc.language.iso | en_US | en_US |
dc.title | An Ultra-low-voltage CMOS VCO Using Parallel Capacitor for Phase Noise Reduction | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | PROCEEDINGS OF PROGRESS IN ELECTROMAGNETICS RESEARCH SYMPOSIUM (PIERS 2012) | en_US |
dc.citation.spage | 1256 | en_US |
dc.citation.epage | 1260 | en_US |
dc.contributor.department | 傳播研究所 | zh_TW |
dc.contributor.department | Institute of Communication Studies | en_US |
dc.identifier.wosnumber | WOS:000327380000264 | - |
顯示於類別: | 會議論文 |