標題: Low-power VCO with phase-noise improvement in 0.18 mu m CMOS technology
作者: Liang, C. -P.
Huang, T. -J.
Rao, P. -Z.
Chung, S. -J.
傳播研究所
Institute of Communication Studies
公開日期: 30-九月-2010
摘要: A low-power 5.25 GHz voltage-controlled oscillator ( VCO) with phase-noise improvement is designed in a 0.18 mu m CMOS 1P6M process. Owing to the use of a larger value of parallel capacitor, an additional harmonic-suppressed capacitor, and an appropriate bulk bias voltage of transistor, a good figure of merit of - 190 dBc/Hz can be achieved without extra chip area and CMOS process steps. The fabricated VCO operates from 5.12 to 5.36 GHz with a core power consumption of 1.9 mW and active chip area of 0.15 mm(2). The measured phase noise at 1 MHz offset is about - 119 dBc/Hz.
URI: http://dx.doi.org/10.1049/el.2010.1278
http://hdl.handle.net/11536/32169
ISSN: 0013-5194
DOI: 10.1049/el.2010.1278
期刊: ELECTRONICS LETTERS
Volume: 46
Issue: 20
起始頁: 1385
結束頁: 1387
顯示於類別:期刊論文


文件中的檔案:

  1. 000282285800020.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。