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dc.contributor.authorChin, Alberten_US
dc.contributor.authorChen, W. B.en_US
dc.contributor.authorChen, P. C.en_US
dc.contributor.authorWu, Y. H.en_US
dc.contributor.authorChi, C. C.en_US
dc.contributor.authorLee, Y. J.en_US
dc.contributor.authorChang-Liao, K. S.en_US
dc.contributor.authorKuan, C. H.en_US
dc.date.accessioned2014-12-08T15:33:16Z-
dc.date.available2014-12-08T15:33:16Z-
dc.date.issued2012en_US
dc.identifier.isbn978-1-4673-2475-5en_US
dc.identifier.urihttp://hdl.handle.net/11536/23151-
dc.description.abstractContinuously down-scaling the operation voltage, saving energy, and maintaining high performance are the major challenge for CMOS device. Small 0.95 similar to 1.4 nm equivalent-oxide thickness (EOT) and 1.4 similar to 2.5X better mobility than universal SiO2/Si data are achieved in metal-gate/high-kappa/Ge CMOS at 1 MV/cm effective field (E-eff). These excellent performances were achieved by using interface engineering and novel process, to overcome the poor high-kappa/Ge interface reaction, low source-drain dopant activation, and n(+)/p ohmic contact. The all-Ge CMOS with measured higher electron and hole mobility has irreplaceable merits of much simpler process, lower cost, and potentially higher yield than the InGaAs-nMOS/Ge-pMOS platform for IC manufacture.en_US
dc.language.isoen_USen_US
dc.titleAdvanced Metal-Gate/High-kappa CMOS with Small EOT and Better High Field Mobilityen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012)en_US
dc.citation.spage51en_US
dc.citation.epage54en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000319824700013-
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