A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design

Abstract

This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-V-t and 0.84 V V-DD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improvement when implemented with a mixed-V-t technology, as compared to that of the classic double-edge-triggered flip-flop design.