標題: A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design
作者: Wang, Li-Rong
Lo, Kai-Yu
Jou, Shyh-Jye
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: double-edge-triggered;flip-flop;level-converting;sense amplifier;mixed threshold voltage
公開日期: 1-Oct-2013
摘要: This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-V-t and 0.84 V V-DD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improvement when implemented with a mixed-V-t technology, as compared to that of the classic double-edge-triggered flip-flop design.
URI: http://dx.doi.org/10.1587/transele.E96.C.1351
http://hdl.handle.net/11536/23317
ISSN: 0916-8524
DOI: 10.1587/transele.E96.C.1351
期刊: IEICE TRANSACTIONS ON ELECTRONICS
Volume: E96C
Issue: 10
起始頁: 1351
結束頁: 1355
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