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dc.contributor.authorShiau, Miin-Shyueen_US
dc.contributor.authorHsu, Heng-Shouen_US
dc.contributor.authorCheng, Ching-Hwaen_US
dc.contributor.authorWeng, Hsiu-Huaen_US
dc.contributor.authorWu, Hong-Chongen_US
dc.contributor.authorLiu, Don-Geyen_US
dc.date.accessioned2014-12-08T15:34:06Z-
dc.date.available2014-12-08T15:34:06Z-
dc.date.issued2013-12-01en_US
dc.identifier.issn0026-2692en_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.mejo.2013.08.019en_US
dc.identifier.urihttp://hdl.handle.net/11536/23432-
dc.description.abstractIn this paper, the charge pump (CP) based on a switches-in-source architecture is to be improved by gain-boosting amplifiers for phase-locked loops (PLLs). In our design, two differential amplifiers were employed in this CP to reduce the effect of the channel length modulation in MOS transistors. As a result, the up and down currents will be rather independent of the output voltage transformed by the capacitive low pass filter (LPF). This circuit was implemented using TSMC 0.18-mu m CMOS technology and was investigated at a power supply of 1.8 V. The measured mismatch was less than 1% for the output voltage ranging from 0.4 to 1.4 V. This result is lower than that of the dynamic current-matching CP with feedback tuning on the same architecture. A comparison will be presented and discussed. (C) 2013 Elsevier Ltd. All rights reserved.en_US
dc.language.isoen_USen_US
dc.subjectPhase-lock loopen_US
dc.subjectCharge pumpen_US
dc.subjectCurrent mismatchen_US
dc.titleReduction of current mismatching in the switches-in-source CMOS charge pumpen_US
dc.typeArticleen_US
dc.identifier.doi10.1016/j.mejo.2013.08.019en_US
dc.identifier.journalMICROELECTRONICS JOURNALen_US
dc.citation.volume44en_US
dc.citation.issue12en_US
dc.citation.spage1296en_US
dc.citation.epage1301en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000329267500031-
dc.citation.woscount0-
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