應用倍頻取樣相位偵測器之鎖相迴路設計

Abstract

本論文提出應用倍頻取樣相位偵測器之鎖相迴路設計。倍頻取樣相位偵測器藉由加倍鎖相迴路之迴路頻寬降低鎖定時間，亦使參考頻雜訊移往高頻來降低參考頻雜訊。在系統分析方面，建立了一鎖相迴路使用倍頻取樣相位偵測器之線性模型。在驗證降低鎖定時間與參考頻雜訊的抑制方面，建立了Verilog-AMS 鎖相迴路使用倍頻取樣相位偵測器與一般相位偵測器之暫態模型。在電路設計方面，設計一鎖相迴路可操作在倍頻取樣相位偵測器或一般相位偵測器模式，輸出頻率切換在 2.88兆赫茲與2.304兆赫茲。在模擬結果中，鎖相迴路之鎖定時間可以降低50﹪在30ppm 的輸出頻率精準度，參考頻雜訊降低16dB且被移往倍頻。

In this thesis, a charge-pump phase-locked loop (PLL) design with double sampling phase detector (DSPD) is proposed. By using the double sampling phase detector, the PLL loop bandwidth is doubled to obtain the fast settling time and meanwhile shift the reference spur to higher frequency to suppress the reference spur. For system analysis, a third-order charge-pump PLL with DSPD linear model is developed. Verilog-AMS charge-pump PLL timing models with DSPD and conventional phase detector (PD) are developed to verify the fast settling time and reference spur suppression. A 2.304 GHz/ 2.88GHz charge-pump PLL with two operation modes, DSPD mode and conventional PD mode, is designed. From the simulation results, the settling time is reduced 50% in 30ppm frequency accuracy and the reference spur is suppressed 16dB.