標題: | 利用鎖相迴路模擬做NRZ訊號之相位偵測器的性能比較 Performance Comparisons of Phase Detectors for NRZ Signals via Simulations of Phase-Locked Loops |
作者: | 古振杰 鄭木火 電控工程研究所 |
關鍵字: | 相位偵測器;頻率偵測器;鎖相迴路;Phase Detector;Frequency Detector;Phase-Locked Loops |
公開日期: | 2004 |
摘要: | 鎖相迴路(Phase-Locked Loops)的應用極為廣泛,已成為許多類比及數位系統的基本元件。在鎖相迴路架構中含有相位偵測器 (Phase Detector)、低通濾波器 (Low Pass Filter)及壓控振盪器(Voltage Controlled Oscillator)共三個功能方塊。其中相位偵測器的功能是用來比較壓控振盪器的輸出訊號與輸入訊號的相位差異。因此相位偵測器的特性常常是影響了整個鎖相迴路效能的關鍵方塊。由於在應用上大部份輸入為 NRZ (non-return to zero) 訊號,因此本論文針對使用在 NRZ信號常用的典型相位偵測器,Alexander相位偵測器及Hogge相位偵測器, 加以探討、分析、改進、及模擬。我們分別分析此二相位偵測器的工作原理及其特性,並比較其之間的優缺點;此外我們也就此二種相位偵測器,分別提出其改進的架構及實現電路以提昇其效能。本論文利用 MATLAB Simulink 的模擬環境下,建立一鎖相迴路的模擬系統以模擬在使用各種不同相位偵測器下,鎖相迴路系統的響應情形,並就其響應速度及穩態誤差加以探討比較。由於一系統在鎖相之前,必須先鎖頻。而常用方法是鎖相及鎖頻相互結合。因此本論文最後並就結合頻率偵測器 (Frequency Detector)的鎖相迴路系統, 探討及模擬在壓控振盪器時脈和 NRZ 訊號有初始頻率差時,鎖相迴路系統的響應。 A phase-locked loop (PLL) has been so widely used that it becomes a basic element in many modern digital or analog systems. A PLL consists of three functional blocks, namely, the phase detector (PD), the loop filter, and the voltage-controlled oscillator (VCO). The PD is used to detect the phase difference between the input signal and the oscillator output of the VCO; the performance of the PD often determines the performance of the PLL. In most applications, the input signals are NRZ (non-return to zero) coded. Hence, in this thesis we focus on two most often used PDs for NRZ signals, the Alexander PD and the Hogge PD, for investigation,analysis, improvement and simulation. We first analyze the characteristics of these two PDs and discuss their differences, then we develop new block diagrams and circuit realizations for improving the PD performances. We also develop a PLL simulation system using the Matlab Simulink to investigate the responses of PLL systems using various PDs; both the response time and the steady-state error are used for comparison and discussion. Since the frequency acquisition (frequency lock) is necessary before the phase lock and the most common realization is to combine the frequency detector with the PD, we further embed the frequency detector into the PLL simulation system and investigate and simulate the response of the system under an initial frequency difference between the VCO output and input signals. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT009212611 http://hdl.handle.net/11536/69068 |
顯示於類別: | 畢業論文 |