標題: Efficient Multiply-by-3 and Divide-by-3 Algorithms and Their Fast Hardware Implementation
作者: Wey, Chin-Long
Jui, Ping-Chang
Sung, Gang-Neng
電機工程學系
Department of Electrical and Computer Engineering
關鍵字: ripple carry adder (RCA);carry-lookahead adder (CLA);ripple-borrow subtractor (RBS);multiplier;divider
公開日期: 1-二月-2014
摘要: This study presents efficient algorithms for performing multiply-by-3 (3N) and divide-by-3 (N/3) operations with the additions and subtractions, respectively. No multiplications and divisions are needed. Full adder (FA) and full subtractor (FS) can be implemented to realize the N3 and N/3 operations, respectively. For fast hardware implementation, this paper introduces two basic cells UCA and UCS for 3N and N/3 operations, respectively. For 3N operation, the UCA-based ripple carry adder (RCA) and carry lookahead adder (CLA) designs are proposed and their speed performances are estimated based on the delay data of standard cell library in TSMC 0.18 mu m CMOS process. Results show that the 16-bit UCA-based RCA is about 3 times faster than the conventional FA-based RCA and even 25% faster than the FA-based CLA. The proposed 16-bit and 64-bit UCA-based CLAs are 62% and 36% faster than the conventional FA-based CLAs, respectively. For N/3 operations, ripple borrow subtractor (RBS) is also presented. The 16-bit UCS-based RBS is about 15.5% faster than the 16-bit FS-based RBS.
URI: http://dx.doi.org/10.1587/transfun.E97.A.616
http://hdl.handle.net/11536/23816
ISSN: 0916-8508
DOI: 10.1587/transfun.E97.A.616
期刊: IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
Volume: E97A
Issue: 2
起始頁: 616
結束頁: 623
顯示於類別:期刊論文


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