標題: | A VLSI Design of Singular Value Decomposition Processor Used in Real-time ICA Computation for Multi-channel EEG System |
作者: | Huang, Kuan-Ju Shih, Wei-Yeh Liao, Jui-Chieh Fang, Wai-Chi 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2013 |
摘要: | This paper presents a VLSI design of singular value decomposition (SVD) processor used in real-time independent component analysis (ICA) computation for multi-channel electroencephalography (EEG) system. EEG signals are easily influenced by other artifacts. To acquire artifact free EEG signals, ICA is a popular method for artifact removal. Results obtained after the pre-processing of ICA are often used for further applications such as brain computer interfaces (BCIs). In order to improve the feasibility and convenience of BCIs, a real-time ICA pre-processing is required. Because SVD is used frequently in computations of ICA, a SVD processor used for real-time ICA computation is essential. This paper aims to develop a custom SVD for multi-channel EEG systems based on ICA. During the ICA process, the proposed processor aims to solve the inverse and inverse square root matrices in real time. And the processor obtains a highly accurate result since a novel design concept for renewing data flow and parallel data processing are provided in this research. This processor is developed with TSMC 90nm CMOS technology in an 8-channel EEG system. The performance of the proposed SVD is also provided with the processing result of the EEG system. |
URI: | http://hdl.handle.net/11536/24131 |
ISBN: | 978-1-4673-5762-3; 978-1-4673-5760-9 |
ISSN: | 0271-4302 |
期刊: | 2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
起始頁: | 413 |
結束頁: | 416 |
Appears in Collections: | Conferences Paper |