標題: Fast Zero Block Detection and Early CU Termination for HEVC Video Coding
作者: Chiang, Pai-Tse
Chang, Tian Sheuan
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2013
摘要: This paper proposed a fast zero block detection for various transform size from 32x32 to 4x4 in the new generation of the High Efficiency Video Coding (HEVC) standard. The derivation is based on sum-of-absolute-difference (SAD) value available in the inter prediction computation. The proposed method achieves detection accuracy to 90% in average, and saves transform unit computation by 44% (QP at 22) and 65% (QP at 32) with negligible coding performance loss, when compared with that of HM4.0rc1. Additionally, this pre-skip detection could further help decide the CU inter mode efficiently with about 50% time saving.
URI: http://hdl.handle.net/11536/24142
ISBN: 978-1-4673-5762-3; 978-1-4673-5760-9
ISSN: 0271-4302
期刊: 2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
起始頁: 1640
結束頁: 1643
顯示於類別:會議論文