Title: Sub-Sampling Charge Pump and Random Pulsewidth Matching Technique for Frequency Synthesizer
Authors: Liao, Te-Wen
Su, Jun-Ren
Hung, Chung-Chih
交大名義發表
National Chiao Tung University
Keywords: PLL;low spur;Synthesizer
Issue Date: 2013
Abstract: This paper presents a frequency synthesizer system with random pulsewidth matching technique and a sub-sampling charge pump. Through the randomization and average of the pulsewidth and the reduction of current mismatch, the frequency synthesizer can reduce the ripples on the control voltage of the voltage-controlled oscillator in order to reduce the reference spur at the output of the phase-locked loop. A random clock generator is used to perform a random selection control. To demonstrate the effectiveness of the proposed spur-reduction techniques, a 2.5GHz to 2.7 GHz FLPLL was designed and fabricated using a TSMC 90nm CMOS process. The proposed circuit can achieve a phase noise of - 114 dBc/Hz at an offset frequency of 1 MHz and reference spurs below - 74 dBc.
URI: http://hdl.handle.net/11536/24158
ISBN: 978-1-4799-0066-4
ISSN: 1548-3746
Journal: 2013 IEEE 56TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)
Begin Page: 1035
End Page: 1038
Appears in Collections:Conferences Paper