完整後設資料紀錄
DC 欄位語言
dc.contributor.authorChang, Ming-Hungen_US
dc.contributor.authorHsieh, Wei-Chihen_US
dc.contributor.authorWu, Pei-Chenen_US
dc.contributor.authorChuang, Ching-Teen_US
dc.contributor.authorChen, Kuan-Nengen_US
dc.contributor.authorWang, Chen-Chaoen_US
dc.contributor.authorTing, Chun-Yenen_US
dc.contributor.authorChen, Kua-Huaen_US
dc.contributor.authorChiu, Chi-Tsungen_US
dc.contributor.authorTong, Ho-Mingen_US
dc.contributor.authorHwang, Weien_US
dc.date.accessioned2014-12-08T15:35:46Z-
dc.date.available2014-12-08T15:35:46Z-
dc.date.issued2013en_US
dc.identifier.isbn978-1-4799-0233-0en_US
dc.identifier.urihttp://hdl.handle.net/11536/24163-
dc.description.abstractIn this work, a multi-layer hierarchical distributed power delivery architecture for TSV 3DIC is proposed. By decoupling global and local power networks, the proposed power delivery architecture can be flexibly configured for different power requests. The decoupled power architectures can also greatly reduce the required decoupling capacitor sizes for voltage stabilization. Meanwhile, a multi-threshold CMOS switched capacitor DC-DC converter with up to 78% power efficiency is implemented in 65nm CMOS for hierarchical distributed power delivery architecture. An adaptive power management technique is presented to work in the local power network to increase the power efficiency. The proposed multi-layer hierarchical distributed power delivery architecture is also very useful for the heterogeneous integration in 3DIC chips.en_US
dc.language.isoen_USen_US
dc.titleMulti-Layer Adaptive Power Management Architecture for TSV 3DIC Applicationsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2013 IEEE 63RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC)en_US
dc.citation.spage1179en_US
dc.citation.epage1185en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000332764900182-
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