完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.author | Liu, Keng-Ming | en_US |
| dc.contributor.author | Peng, Fan-I | en_US |
| dc.contributor.author | Peng, Kang-Ping | en_US |
| dc.contributor.author | Lin, Horng-Chih | en_US |
| dc.contributor.author | Huang, Tiao-Yuan | en_US |
| dc.date.accessioned | 2014-12-08T15:36:06Z | - |
| dc.date.available | 2014-12-08T15:36:06Z | - |
| dc.date.issued | 2014-05-01 | en_US |
| dc.identifier.issn | 0268-1242 | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1088/0268-1242/29/5/055001 | en_US |
| dc.identifier.uri | http://hdl.handle.net/11536/24452 | - |
| dc.description.abstract | In this study, novel n-type double-gate (DG) junction-less (J-less) polycrystalline silicon (poly-Si) nanostrip transistors with different channel doping concentrations (N-C) have been fabricated and investigated. The effects of channel doping concentration on device characteristics were examined comprehensively in this work. The experimental data show that as the channel doping concentration of the J-less device increases, the threshold voltage (V-TH) becomes more negative. Besides, the drain-induced barrier lowering and the subthreshold swing of the J-less transistors become larger as the channel doping increases. We also found that as the channel doping increases, the off-current (I-OFF) increases and the on-current (I-ON) actually decreases due to the doping-dependent mobility degradation. The conduction mechanisms under different channel doping concentrations were also investigated by TCAD simulation. The experimental results suggest that the n-type DG nanostrip J-less transistor with lower channel doping will have superior device characteristics. | en_US |
| dc.language.iso | en_US | en_US |
| dc.subject | double gate | en_US |
| dc.subject | channel doping | en_US |
| dc.subject | junction-less transistor | en_US |
| dc.subject | poly-Si | en_US |
| dc.subject | nanowire | en_US |
| dc.title | The effects of channel doping concentration for n-type junction-less double-gate poly-Si nanostrip transistors | en_US |
| dc.type | Article | en_US |
| dc.identifier.doi | 10.1088/0268-1242/29/5/055001 | en_US |
| dc.identifier.journal | SEMICONDUCTOR SCIENCE AND TECHNOLOGY | en_US |
| dc.citation.volume | 29 | en_US |
| dc.citation.issue | 5 | en_US |
| dc.citation.epage | en_US | |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.identifier.wosnumber | WOS:000336167700011 | - |
| dc.citation.woscount | 0 | - |
| 顯示於類別: | 期刊論文 | |

