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dc.contributor.authorHu, Vita Pi-Hoen_US
dc.contributor.authorFan, Ming-Longen_US
dc.contributor.authorHsieh, Chien-Yuen_US
dc.contributor.authorSu, Pinen_US
dc.contributor.authorChuang, Ching-Teen_US
dc.date.accessioned2014-12-08T15:36:11Z-
dc.date.available2014-12-08T15:36:11Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-4244-7701-2en_US
dc.identifier.issn1946-1569en_US
dc.identifier.urihttp://hdl.handle.net/11536/24546-
dc.description.abstractThis paper analyzes the impact of intrinsic process variation and NBTI/PBTI induced time-dependent variations on the stability/variability of 6T FinFET SRAM cells with various surface orientations. Due to quantum confinement, (110)-oriented pull-down devices with fin Line Edge Roughness (LER) show larger Vread,0 and Vtrip variations, thus degrading RSNM and its variability. (100)-oriented pull-up devices with fin LER show larger Vwrite,0 and Vtrip variations, hence degrade the variability of WSNM. The combined effects of intrinsic process variation and NBTI/PBTI induced variations have been examined to optimize the FinFET SRAM cells. Pull-up devices with (110) orientation suffer larger NBTI, resulting in large Vtrip variation and significant degradation of RSNM. Our study indicates that consideration of NBTI/PBTI induced temporal variation changes the optimal choice of FinFET SRAM cell surface orientations in term of mu RSNM/sigma RSNM.en_US
dc.language.isoen_USen_US
dc.titleFinFET SRAM Cell Optimization Considering Temporal Variability due to NBTI/PBTI and Surface Orientationen_US
dc.typeArticleen_US
dc.identifier.journalSISPAD 2010 - 15TH INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICESen_US
dc.citation.spage269en_US
dc.citation.epage272en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000283778800013-
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