A 40 nm 0.32 V 3.5 MHz 11T Single-Ended Bit-Interleaving Subthreshold SRAM with Data-Aware Write-Assist

Abstract

This paper presents a new bit-interleaving 11T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to mitigate the leakage and variation and improve the Write-ability in deep sub-100nm technology. Measurement results from a 4 Kb test chip implemented in 40 nm General Purpose (40GP) CMOS technology operates for V-DD down to 0.32 V (similar to 0.69X of threshold voltage) with V-DDMIN limited by Read operation. The measured maximum operation frequency is 3.5 MHz (16.5 MHz) at 0.32 V (0.38 V) with total power consumption of 15.2 mu W (27.2 mu W) at 25 degrees C.