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dc.contributor.authorChou, Chia-Hsinen_US
dc.contributor.authorLee, I-Cheen_US
dc.contributor.authorLei, Dai-Cheen_US
dc.contributor.authorCheng, Huang-Chungen_US
dc.date.accessioned2014-12-08T15:36:19Z-
dc.date.available2014-12-08T15:36:19Z-
dc.date.issued2014-06-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.7567/JJAP.53.06JE07en_US
dc.identifier.urihttp://hdl.handle.net/11536/24664-
dc.description.abstractIn this letter, single-and double-gate (SG and DG) planar junctionless (JL) thin-film transistors fabricated via a simple process with an in situ-doped active layer is discussed. The DG structure demonstrated a superior subthreshold swing of 160mV/dec and a lower off-current of 1.3 x 10(-13)A than those of 329mV/dec and 2.1 x 10(-12)A for the SG structure, respectively. It contributes to the enhancement of the gate controllability and ultrathin channel. Consequently, the simple fabrication process of the DG JL device is suitable for future application on system-on-panel and three-dimensional integrated circuits. (C) 2014 The Japan Society of Applied Physicsen_US
dc.language.isoen_USen_US
dc.titlePlanar junctionless poly-Si thin-film transistors with single gate and double gateen_US
dc.typeArticleen_US
dc.identifier.doi10.7567/JJAP.53.06JE07en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICSen_US
dc.citation.volume53en_US
dc.citation.issue6en_US
dc.citation.epageen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000338439500026-
dc.citation.woscount0-
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