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dc.contributor.authorChang, Hsiu-Chien_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.date.accessioned2014-12-08T15:36:20Z-
dc.date.available2014-12-08T15:36:20Z-
dc.date.issued2014-06-01en_US
dc.identifier.issn0090-6778en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCOMM.2014.2320508en_US
dc.identifier.urihttp://hdl.handle.net/11536/24679-
dc.description.abstractThis paper presents two iterative decoding algorithms for a class of non-binary two-step majority-logic (NB-TS-MLG) decodable cyclic codes. A partial parallel decoding scheme is also introduced to provide a balanced trade-off between decoding speed and storage requirements. Unlike non-binary one-step MLG decodable cyclic codes, the Tanner graphs of which are 4-cycle-free, NB-TS-MLG decodable cyclic codes contain a large number of short cycles of length 4, which tend to degrade decoding performance. The proposed algorithms utilize the orthogonal structure of the parity-check matrices of the codes to resolve the degrading effects of the short cycles of length 4. Simulation results demonstrate that the NB-TS-MLG decodable cyclic codes decoded with the proposed algorithms offer coding gains as much as 2.5 dB over Reed-Solomon codes of the same lengths and rates decoded with either hard-decision or algebraic soft decision decoding.en_US
dc.language.isoen_USen_US
dc.subjectExtended min-sum algorithmen_US
dc.subjectmajority-logic decodingen_US
dc.subjectnon-binary LDPC codesen_US
dc.subjectcyclic codesen_US
dc.titleIterative Decoding Algorithms for a Class of Non-Binary Two-Step Majority-Logic Decodable Cyclic Codesen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCOMM.2014.2320508en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMMUNICATIONSen_US
dc.citation.volume62en_US
dc.citation.issue6en_US
dc.citation.spage1779en_US
dc.citation.epage1789en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000338029200003-
dc.citation.woscount0-
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