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dc.contributor.authorLin, Chun-Yuen_US
dc.contributor.authorFan, Mei-Lianen_US
dc.date.accessioned2014-12-08T15:36:21Z-
dc.date.available2014-12-08T15:36:21Z-
dc.date.issued2014-06-01en_US
dc.identifier.issn1530-4388en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TDMR.2014.2311130en_US
dc.identifier.urihttp://hdl.handle.net/11536/24688-
dc.description.abstractThe diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than V-DD or lower than V-SS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.en_US
dc.language.isoen_USen_US
dc.subjectDiodeen_US
dc.subjectelectrostatic discharge (ESD)en_US
dc.subjectlayouten_US
dc.subjectstackupen_US
dc.titleOptimization on Layout Style of Diode Stackup for On-Chip ESD Protectionen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TDMR.2014.2311130en_US
dc.identifier.journalIEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITYen_US
dc.citation.volume14en_US
dc.citation.issue2en_US
dc.citation.spage775en_US
dc.citation.epage777en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000337132200027-
dc.citation.woscount1-
Appears in Collections:Articles


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