標題: | Gate-all-around floating-gate memory device with triangular poly-Si nanowire channels |
作者: | Tsai, Jung-Ruey Lee, Ko-Hui Lin, Horng-Chih Huang, Tiao-Yuan 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 1-四月-2014 |
摘要: | A novel gate-all-around (GAA) poly-Si floating-gate (FG) memory device with triangular nanowire (NW) channels was fabricated and characterized in this work. The enhanced electric field around the corners of the NW channels boosts more electrons tunneling through the tunnel oxide layer during programming and erasing (P/E) processes, and thus the operation voltage markedly decreases. Furthermore, the nonlocalized trapping feature characteristic of the FG makes the injection of electrons easier during the programming operation, which was demonstrated by technology computer-aided design (TCAD) simulations. (C) 2014 The Japan Society of Applied Physics |
URI: | http://dx.doi.org/10.7567/JJAP.53.04ED14 http://hdl.handle.net/11536/24751 |
ISSN: | 0021-4922 |
DOI: | 10.7567/JJAP.53.04ED14 |
期刊: | JAPANESE JOURNAL OF APPLIED PHYSICS |
Volume: | 53 |
Issue: | 4 |
結束頁: | |
顯示於類別: | 期刊論文 |