標題: Effect of Low Temperature Ge Seed Layer and Post Thermal Annealing on Quality of Ge1-xSix (0.05 <= x <= 0.1) Graded Buffer Layers by UHV-CVD
作者: Chi-Lang Nguyen
Nguyen Hong Quan
Binh-Tinh Tran
Su, Yung-Hsuan
Tang, Shih-Hsuan
Luo, Guang-Li
Chang, Edward-Yi
材料科學與工程學系
電子工程學系及電子研究所
奈米中心
Department of Materials Science and Engineering
Department of Electronics Engineering and Institute of Electronics
Nano Facility Center
關鍵字: Ge;SiGe;UHV/CVD;fully stress relaxation
公開日期: 1-七月-2014
摘要: High crystal quality, smooth surface and fully relaxed Ge1-xSix (0.05 <= x <= 0.1) buffers are grown on 6 degrees-off (100) Si substrate by UHV-CVD. A low-temperature (LT) Ge seed layer is used to improve the quality of the Ge1-xSix buffers. In this study, the LT-Ge seed layer is deposited directly onto the Si substrate at a low temperature of 315 degrees C. After that, stress-free Si0.1Ge0.9 and Si0.05Ge0.95 layers are grown, respectively. An in-situ annealing process is also performed for the Si0.1Ge0.9/LT-Ge layers to increase the degree of relaxation. The total thickness of the epitaxial layer is 270 nm, with the average surface roughness at 0.6 nm.
URI: http://dx.doi.org/10.1007/s13391-014-4016-7
http://hdl.handle.net/11536/24894
ISSN: 1738-8090
DOI: 10.1007/s13391-014-4016-7
期刊: ELECTRONIC MATERIALS LETTERS
Volume: 10
Issue: 4
起始頁: 759
結束頁: 762
顯示於類別:期刊論文