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dc.contributor.authorChao, Mango C. -T.en_US
dc.contributor.authorChin, Ching-Yuen_US
dc.contributor.authorLin, Chen-Weien_US
dc.date.accessioned2014-12-08T15:37:44Z-
dc.date.available2014-12-08T15:37:44Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-4244-8192-7en_US
dc.identifier.issn1933-7760en_US
dc.identifier.urihttp://hdl.handle.net/11536/25942-
dc.identifier.urihttp://dx.doi.org/10.1109/ICCAD.2010.5654154en_US
dc.description.abstractDefect repair has become a necessary process to enhance the overall yield for memories since manufacturing a natural good memory is difficult in current memory technologies. This paper presents an yield-estimation scheme, which utilizes an induction-based approach to calculate the probability that all defects in a memory can be successfully repaired by a two-dimensional redundancy design. Unlike previous works, which rely on a time-consuming simulation to estimate the expected yield, our yield-estimation scheme only requires scalable mathematical computation and can achieve a high accuracy with limited time and space complexity. Also, the proposed estimation scheme can consider the impact of single defects, column defects, and row defects simultaneously. With the help of the proposed yield-estimation scheme, we can effectively identify the most profitable redundancy configuration for large memory designs within few seconds while it may take several hours or even days by using conventional simulation approach.en_US
dc.language.isoen_USen_US
dc.titleMathematical Yield Estimation for Two-Dimensional-Redundancy Memory Arraysen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/ICCAD.2010.5654154en_US
dc.identifier.journal2010 IEEE AND ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD)en_US
dc.citation.spage235en_US
dc.citation.epage240en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000287997600038-
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