標題: Impact of Strain Layer on Gate Leakage and Interface-State for nMOSFETs Fabricated by Stress-Memorization Technique
作者: Liao, Chia-Chun
Lin, Min-Chen
Chiang, Tsung-Yu
Chao, Tien-Sheng
電子物理學系
Department of Electrophysics
公開日期: 2011
摘要: This paper investigates the impact of stress memorization on the interface-state for n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETS). We found that both the initial component of the deposited capping layer and the H released during annealing affected interface-state passivation. The annealed stress is responsible for degraded gate-leakage characteristics. Based on electrical performance and gate leakage, an initial compressive layer of SiN performs better than an initial tensile layer for the stress-memorization technique process. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3506399] All rights reserved.
URI: http://hdl.handle.net/11536/26193
http://dx.doi.org/10.1149/1.3506399
ISSN: 1099-0062
DOI: 10.1149/1.3506399
期刊: ELECTROCHEMICAL AND SOLID STATE LETTERS
Volume: 14
Issue: 1
起始頁: II30
結束頁: II32
顯示於類別:期刊論文