A High Throughput VLSI Design with Hybrid Memory Architecture for H.264/AVC CABAC Decoder

Abstract

A high throughput context-based adaptive binary arithmetic coding (CABAC) decoding design with hybrid memory architecture for H.264/AVC is presented in this paper. To accelerate the decoding speed with hardware cost consideration, a new hybrid memory two-symbol parallel decoding technique is proposed. In addition, an efficient mathematical transform method is also proposed to further decrease the critical path of two-symbol binary arithmetic decoding procedure. The proposed architecture is implemented by UMC 90nm technology and experimental results show that our proposal can operate at 264 MHz with 42.37k gate count, and the throughput is 483.1 Mbins/sec, which surpasses previous design with 48.6% hardware cost saving.