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dc.contributor.authorLiao, Yuan-Hsinen_US
dc.contributor.authorLi, Gwo-Longen_US
dc.contributor.authorChang, Tian-Sheuanen_US
dc.date.accessioned2014-12-08T15:38:37Z-
dc.date.available2014-12-08T15:38:37Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-4244-5309-2en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/26421-
dc.description.abstractA high throughput context-based adaptive binary arithmetic coding (CABAC) decoding design with hybrid memory architecture for H.264/AVC is presented in this paper. To accelerate the decoding speed with hardware cost consideration, a new hybrid memory two-symbol parallel decoding technique is proposed. In addition, an efficient mathematical transform method is also proposed to further decrease the critical path of two-symbol binary arithmetic decoding procedure. The proposed architecture is implemented by UMC 90nm technology and experimental results show that our proposal can operate at 264 MHz with 42.37k gate count, and the throughput is 483.1 Mbins/sec, which surpasses previous design with 48.6% hardware cost saving.en_US
dc.language.isoen_USen_US
dc.titleA High Throughput VLSI Design with Hybrid Memory Architecture for H.264/AVC CABAC Decoderen_US
dc.typeArticleen_US
dc.identifier.journal2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMSen_US
dc.citation.spage2007en_US
dc.citation.epage2010en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000287216002057-
Appears in Collections:Conferences Paper