標題: A software/hardware cooperated stack operations folding model for Java processors
作者: Ton, LR
Chang, LC
Shann, JJ
Chung, CP
資訊工程學系
Department of Computer Science
關鍵字: Java processor;stack operations folding;POC folding model;T-POC folding model;T-POC bytecode rescheduler
公開日期: 1-八月-2004
摘要: Java has become the most important language in the Internet area, but the execution performance of Java processors is severely limited by the true data dependency inherited from the stack architecture defined by Sun's Java Virtual Machine. A sequential hardware-based folding algorithm-POC folding model was proposed in the earlier research to eliminate up to 80.1% of stack push and pop bytecodes. The remaining stack push and pop bytecodes cannot be folded due to the sequential checking characteristic of the POC folding model. In this paper, a new software/hardware cooperated folding algorithm-T-POC (Tagged-POC) folding model is proposed to enhance the folding ability of the POC-based Java processors to fold the remaining stack push and pop bytecodes. While executing the bytecodes, bytecode grouping and rescheduling are done by a T-POC bytecode rescheduler to generate the new binary class images in memory. With the cooperation of the hardware-based POC folding model, higher execution performance can be achieved by executing the newly generated class images. Statistical data show that 94.8% of stack push and pop bytecodes can be folded, and the overall execution speedups of 2-, 3-, and 4-foldable strategies are 1.72, 1.73 and 1.74, respectively, as compared to a single-pipelined stack machine without folding. (C) 2003 Elsevier Inc. All rights reserved.
URI: http://dx.doi.org/10.1016/S0164-1212(03)00100-6
http://hdl.handle.net/11536/26538
ISSN: 0164-1212
DOI: 10.1016/S0164-1212(03)00100-6
期刊: JOURNAL OF SYSTEMS AND SOFTWARE
Volume: 72
Issue: 3
起始頁: 377
結束頁: 387
顯示於類別:期刊論文


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