完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Guo, JC | en_US |
dc.contributor.author | Lien, WY | en_US |
dc.contributor.author | Tsai, TL | en_US |
dc.contributor.author | Chen, SM | en_US |
dc.contributor.author | Wu, CM | en_US |
dc.date.accessioned | 2014-12-08T15:39:18Z | - |
dc.date.available | 2014-12-08T15:39:18Z | - |
dc.date.issued | 2004-05-01 | en_US |
dc.identifier.issn | 0018-9383 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TED.2004.826884 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/26844 | - |
dc.description.abstract | High-performance analog/digital elements have been successfully fabricated bya 0.13-mum low-kappa-Cu logic-based mixed-signal CMOS process in a single chip to enable a 2.1-Gb/s read-channel for hard disk drives that is a record-high data rate supported by fully CMOS solution. The high-performance analog devices demonstrate superior drivability, matching, noise immunity, and reliability by a unique dual-gate oxide module to support the aggressive oxide thickness scaling and maintain promisingly good reliability in all aspects. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | dual-gate oxide | en_US |
dc.subject | high-performance analog (HPA) | en_US |
dc.subject | read-channel | en_US |
dc.title | 0.13-mu m low-kappa-Cu CMOS logic-based technology for 2.1-Gb high data rate read-channel | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TED.2004.826884 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | en_US |
dc.citation.volume | 51 | en_US |
dc.citation.issue | 5 | en_US |
dc.citation.spage | 757 | en_US |
dc.citation.epage | 763 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000221117300016 | - |
dc.citation.woscount | 3 | - |
顯示於類別: | 期刊論文 |