標題: | Active electrostatic discharge (ESD) device for on-chip ESD protection in sub-quarter-micron complementary metal-oxide semiconductor (CMOS) process |
作者: | Ker, MD Tseng, TK 電機學院 College of Electrical and Computer Engineering |
關鍵字: | electrostatic discharge (ESD);threshold voltage;active ESD device;leakage current |
公開日期: | 15-一月-2004 |
摘要: | A novel electrostatic discharge (ESD) protection device with a threshold voltage of similar to0V for complementary metal-oxide semiconductor (CMOS) integrated circuits in sub-quarter-micron CMOS technology is proposed. Quite different to the traditional ESD protection devices, such an active ESD device is originally standing in its turn-on state when the IC is zapped under ESD events. Therefore, such an active ESD device has the fastest turn-on speed and the lowest turn-on voltage to effectively protect the internal circuits with a much thinner gate oxide in future sub-0.1 mum CMOS technology. The proposed active ESD device is fully process-compatible to the general sub-quarter-micron CMOS process. |
URI: | http://dx.doi.org/10.1143/JJAP.43.L33 http://hdl.handle.net/11536/27136 |
ISSN: | 0021-4922 |
DOI: | 10.1143/JJAP.43.L33 |
期刊: | JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS |
Volume: | 43 |
Issue: | 1A-B |
起始頁: | L33 |
結束頁: | L35 |
顯示於類別: | 期刊論文 |