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dc.contributor.authorWu, CYen_US
dc.contributor.authorLiow, YYen_US
dc.date.accessioned2014-12-08T15:39:47Z-
dc.date.available2014-12-08T15:39:47Z-
dc.date.issued2004-01-01en_US
dc.identifier.issn1057-7122en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSI.2003.821277en_US
dc.identifier.urihttp://hdl.handle.net/11536/27173-
dc.description.abstractIn this paper, two new architectures for high-speed CMOS wave-pipelined current-mode A/D converters (WP-IADCs) are proposed and analyzed. In the new WP-IADC architectures, the wave-pipelined theory is applied to both pipeline structures, called full WP-IADC (FWP-IADC) and indirect transfer WP-IADC (ITWP-IADC). In the FWP-IADC, each stage uses the full current-mode wave-pipelined structure without switched-current cell circuits. In the ITWP-IADC, the switched-current cells are incorporated into the wave-pipelined stages which are divided into several sections with controlled clocks. Therefore, the proposed ITWP-IADC performs optimally in terms of speed and accuracy in the WP-IADCs. Generally, the proposed WP-IADCs have the advantages of high speed, high input frequency, high efficiency of timing usage, high clock-period flexibility in switched-current cells for precision enhancement, and reduced number of switched-current cells in the overall data path for linearity improvement. According to the theoretical analysis on the proposed WP-IADC structures, the minimum sampling clock period is proportional to the intrinsic delay of the current mirror and the increased rise/fall time in each wave-pipelined stage. The HSPICE simulation results reveal that, under Nyquist rate sampling in 8-b resolution, a sampling rate of 20 and 54 MHz can be achieved for FWP-IADC and two-section ITWP-LADC, respectively. If four wave-pipelined sections are used, the ITWP-IADC can be operated at 166 MHz at an input frequency of 8 MHz. To experimentally verify the correct function of the proposed WP-IADC structures, the proposed new architecture of the FWP-IADC is implemented by using 0.35-mum CMOS technology. The measurement results successfully demonstrate the feasibility of wave-pipelined IADC architectures in applications of high-speed ADCs.en_US
dc.language.isoen_USen_US
dc.subjectCMOS technologyen_US
dc.subjectcurrent-mode A/D converteren_US
dc.subjectswitched-current cellen_US
dc.subjectwave pipelineden_US
dc.titleNew current-mode wave-pipelined architectures for high-speed analog-to-digital convertersen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSI.2003.821277en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERSen_US
dc.citation.volume51en_US
dc.citation.issue1en_US
dc.citation.spage25en_US
dc.citation.epage37en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000220147500003-
dc.citation.woscount10-
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