完整後設資料紀錄
DC 欄位語言
dc.contributor.authorLee, Yu-Hueien_US
dc.contributor.authorChen, Ke-Horngen_US
dc.date.accessioned2014-12-08T15:39:48Z-
dc.date.available2014-12-08T15:39:48Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-4244-7773-9en_US
dc.identifier.issn1548-3746en_US
dc.identifier.urihttp://hdl.handle.net/11536/27187-
dc.description.abstractThis proposed 65 nm sub-1V multi-stage low-dropout (LDO) regulator aims to integrate of power management for SoC systems. The multi-stage structure can derive the high dc voltage gain from the short-channel core devices to insure the load/line regulation. The inserted flying capacitor used to separate the high-frequency non-dominant poles can increase the system phase margin. Moreover, a dynamic gain adjusting (DGA) mechanism can adjust the dc voltage gain based on the load condition to ensure the LDO operation at ultra light loads. The correct operation under sub-1V condition is achieved with 65 nm low-power core devices. Simulated load transient response shows the voltage recovery time is within 0.6 mu s when load current changes from 50 mu A to 100 mA and vice versa.en_US
dc.language.isoen_USen_US
dc.titleA 65nm Sub-1V Multi-Stage Low-Dropout (LDO) Regulator Design for SoC Systemsen_US
dc.typeArticleen_US
dc.identifier.journal53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMSen_US
dc.citation.spage584en_US
dc.citation.epage587en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000287099800146-
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