完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lee, Yu-Huei | en_US |
dc.contributor.author | Chen, Ke-Horng | en_US |
dc.date.accessioned | 2014-12-08T15:39:48Z | - |
dc.date.available | 2014-12-08T15:39:48Z | - |
dc.date.issued | 2010 | en_US |
dc.identifier.isbn | 978-1-4244-7773-9 | en_US |
dc.identifier.issn | 1548-3746 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/27187 | - |
dc.description.abstract | This proposed 65 nm sub-1V multi-stage low-dropout (LDO) regulator aims to integrate of power management for SoC systems. The multi-stage structure can derive the high dc voltage gain from the short-channel core devices to insure the load/line regulation. The inserted flying capacitor used to separate the high-frequency non-dominant poles can increase the system phase margin. Moreover, a dynamic gain adjusting (DGA) mechanism can adjust the dc voltage gain based on the load condition to ensure the LDO operation at ultra light loads. The correct operation under sub-1V condition is achieved with 65 nm low-power core devices. Simulated load transient response shows the voltage recovery time is within 0.6 mu s when load current changes from 50 mu A to 100 mA and vice versa. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A 65nm Sub-1V Multi-Stage Low-Dropout (LDO) Regulator Design for SoC Systems | en_US |
dc.type | Article | en_US |
dc.identifier.journal | 53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS | en_US |
dc.citation.spage | 584 | en_US |
dc.citation.epage | 587 | en_US |
dc.contributor.department | 電控工程研究所 | zh_TW |
dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
dc.identifier.wosnumber | WOS:000287099800146 | - |
顯示於類別: | 會議論文 |