標題: A 30 V high voltage NMOS structure design in standard 5 VCMOS processes
作者: Lin, TC
Wu, JC
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: standard CMOS processes;high voltage NMOS;breakdown voltage
公開日期: 1-Nov-2003
摘要: This paper describes the robust design of the 30 V high voltage NMOS (HVNMOS) structure implemented in a 0.6 mum 5 V standard CMOS processes without any additional masks or process steps. The structure makes use of the field oxide (FOX) and light doping N-well to increase the drain to gate and drain to bulk breakdown voltages, respectively. By varying the six spacing parameters: the channel length, gate overlap FOX, N-well overlap channel length, poly to the active area of the drain (OD2), metal extend beyond the OD2 and N-well extend beyond the OD2 in HVNMOS structure. the breakdown voltage can be improved. The experimental results show that the breakdown voltage of the normal NMOS is 11V, and the breakdown voltage of the HVNMOS is increased to over 30 V. With the optimized layout parameters of the HVNMOS, it can be increased to 38 V.
URI: http://hdl.handle.net/11536/27395
ISSN: 0916-8524
期刊: IEICE TRANSACTIONS ON ELECTRONICS
Volume: E86C
Issue: 11
起始頁: 2341
結束頁: 2345
Appears in Collections:Articles