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dc.contributor.authorHu, GRen_US
dc.contributor.authorHuang, TJen_US
dc.contributor.authorWu, YSen_US
dc.date.accessioned2014-12-08T15:40:34Z-
dc.date.available2014-12-08T15:40:34Z-
dc.date.issued2003-08-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.1143/JJAP.42.L895en_US
dc.identifier.urihttp://hdl.handle.net/11536/27683-
dc.description.abstractElectroless Pd plating induced crystallization of amorphous silicon (a-Si) thin films has been proposed for fabricating low-temperature polycrystalline silicon thin film transistors (LTPS TFTs). However, the current crystallization process often leads to poor device performance due to the large amount of I'd-silicide residues in the poly-Si thin films. It was found that the amount of I'd silicide increased with annealing time and temperature. In this study, a two-step annealing process was developed to obtain the appropriate amount of Pd silicide for inducing the crystallization of a-Si. The device characteristics were significantly improved by this two-step process.en_US
dc.language.isoen_USen_US
dc.subjectthin-film transistoren_US
dc.subjectamorphous siliconen_US
dc.subjectpolycrystalline siliconen_US
dc.subjectmetal-induced crystallizationen_US
dc.subjectelectroless plating and physical vapor depositionen_US
dc.titleImproved annealing process for electroless Pd plating induced crystallization of amorphous siliconen_US
dc.typeArticleen_US
dc.identifier.doi10.1143/JJAP.42.L895en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERSen_US
dc.citation.volume42en_US
dc.citation.issue8Aen_US
dc.citation.spageL895en_US
dc.citation.epageL897en_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.identifier.wosnumberWOS:000184782600006-
dc.citation.woscount1-
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