標題: Enhanced negative substrate bias degradation in nMOSFETs with ultrathin plasma nitrided oxide
作者: Perng, TH
Chien, CH
Chen, CW
Lin, HC
Chang, CY
Huang, TY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: paramagnetic electron trap;plasma nitrided gate dielectric;substrate hot electron
公開日期: 1-五月-2003
摘要: The degradation induced by substrate hot electron (SHE) injection in 0.13-mum nMOSFETs with ultrathin (similar to2.0 - nm) plasma nitrided gate dielectric was studied. Compared to the conventional thermal oxide, the ultrathin nitrided gate dielectric is found to be more vulnerable to SHE stress, resulting in enhanced threshold voltage (V-t) shift and transconductance (G(m)) reduction. The severity of the enhanced degradation increases with increasing nitrogen content in gate dielectric with prolonged nitridation time. While the SHE-induced degradation is found to be strongly related to the injected electron energy for both conventional oxide [1], [2]and plasma-nitrided oxide, dramatic degradation in threshold voltage shift for nitrided oxide is found to occur at a lower substrate bias magnitude (- - 1 V), compared to thermal oxide (similar to -1.5 V). This enhanced degradation by negative substrate bias in nMOSFETs with plasma-nitrided gate dielectric is attributed to a higher concentration of paramagnetic electron trap precursors introduced during plasma nitridation [3].
URI: http://dx.doi.org/10.1109/LED.2003.812556
http://hdl.handle.net/11536/27940
ISSN: 0741-3106
DOI: 10.1109/LED.2003.812556
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 24
Issue: 5
起始頁: 333
結束頁: 335
顯示於類別:期刊論文


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