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dc.contributor.authorTu, SWen_US
dc.contributor.authorShen, WZen_US
dc.contributor.authorChang, YWen_US
dc.contributor.authorChen, TCen_US
dc.contributor.authorJou, JYen_US
dc.date.accessioned2014-12-08T15:41:09Z-
dc.date.available2014-12-08T15:41:09Z-
dc.date.issued2003-04-01en_US
dc.identifier.issn0925-1030en_US
dc.identifier.urihttp://dx.doi.org/10.1023/A:1023425621006en_US
dc.identifier.urihttp://hdl.handle.net/11536/27999-
dc.description.abstractAs the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are field-solvers, which are intrinsically more accurate but computationally expensive. Others focus on modeling the inductances of special routing topologies such as the bus structure. Therefore, it is not suitable to incorporate them on-line into a layout ( placement and routing) tool for inductance ( delay and noise) optimization. In this paper, we consider the overlapping of unequal wire lengths and dimensions to efficiently extract the loop inductance from the coplanar interconnect structure. The difference between our simulation results and the estimation values obtained by FastHenry [12] is within 10% for practical cases. In particular, our modeling is extremely efficient, and thus can be incorporated into a layout tool for inductance optimization.en_US
dc.language.isoen_USen_US
dc.subjectinductanceen_US
dc.subjectmutual inductanceen_US
dc.subjectself inductanceen_US
dc.subjectmodelingen_US
dc.subjectsimulationen_US
dc.subjectlayouten_US
dc.subjectinterconnecten_US
dc.titleInductance modeling for on-chip interconnectsen_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.doi10.1023/A:1023425621006en_US
dc.identifier.journalANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSINGen_US
dc.citation.volume35en_US
dc.citation.issue1en_US
dc.citation.spage65en_US
dc.citation.epage78en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000182319100007-
Appears in Collections:Conferences Paper


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