深次微米導線之電感模型

Abstract

在設計深次微米電路時，當電路工作頻率達到某個程度以上時，如十億赫茲，由電感造成的雜訊與延遲效應便不能再被忽視。然而目前文獻上的研究對於萃取電感的方法皆傾向於使用複雜的公式來推導，這種方式雖然能萃取出較準確的電感值，但卻極為耗時；除此，另有文獻針對特殊的結構來建立電感模型（如匯流排等）。其考慮之結構中，所有導線皆具相同的寬度與長度。因此，這些模型不適於整合到置放（placement）與繞線（routing）工具內進行電感（包括對延遲與雜訊的效應）最佳化。在本論文中，我們首先提出一個電感模型，此模型能同時考慮導線本身的長度與寬度及導線間的重疊長度，來快速的萃取出共平面連線結構的自感與互感值。實驗顯示，我們的模型與知名的FastHenry所萃取出的電感值相比，誤差在百分之十以內；而我們萃取的速度較之FastHenry有顯著的提升，例如在萃取兩千微米長導線間的感應電感，我們使用Mathematica在Celeron 566 MHz的中央處理器、128 MB的主記憶體的個人電腦上只需要至多0.11秒的時間，然而FastHenry在SUN Sparc Ultra 60（450 MHz）的雙中央處理器、2 GB的主記憶體的工作站上卻需要141秒。由此可見，我們所建立的模型確實適於整合到置放與繞線工具內做電感最佳化。此外，我們也根據對電感特性的研究，提多各種可以減少電感的繞線方式。

As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are field-solvers, which are intrinsically more accurate but computationally expensive. Others focus on modeling the inductances of special routing topologies such as the bus structure, in which all signal wires are of equal dimensions and lengths. Therefore, it is not suitable to incorporate them on-line into a layout (placement and routing) tool for inductance (delay and noise) optimization. In this thesis, we present the first work that considers the overlapping of unequal wire lengths and dimensions to efficiently extract the self and coupling inductance from the coplanar interconnect structure. The difference between our simulation results and those obtained by the famous field-solver FastHenry [15] is within 10% for practical cases. In particular, our method is extremely fast. For example, the running time for extracting the coupling inductance of two wires of 2000 mm by using our analytical formulas is typically within 0.11 seconds using Mathematica on a 566 MHz Cerelon PC with 128 MB RAM while FastHenry requires 141 seconds on SUN Sparc Ultra 60 with dual CPUs (450 MHz each) and 2GB memory. Therefore, it is feasible to incorporate our model into a layout tool on-line. Based on our study, we also suggest several routing topologies for inductance minimization.