A low-power design for Reed-Solomon decoders

doi:10.1142/S0218126603000726

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chang, HC	en_US
dc.contributor.author	Lee, CY	en_US
dc.date.accessioned	2014-12-08T15:41:12Z	-
dc.date.available	2014-12-08T15:41:12Z	-
dc.date.issued	2003-04-01	en_US
dc.identifier.issn	0218-1266	en_US
dc.identifier.uri	http://dx.doi.org/10.1142/S0218126603000726	en_US
dc.identifier.uri	http://hdl.handle.net/11536/28025	-
dc.description.abstract	In this paper, a low-power design for the Reed-Solomon (RS) decoder is presented. Our approach includes a novel two-stage syndrome calculator that reduces the syndrome computations by one-half, a modified Berlekamp-Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The test chip for (255,239) and (208,192) RS decoders are implemented by 0.25 mum CMOS 1P5M and 0.35 mum CMOS SPQM standard cells, respectively. Simulation results show our approach can work successfully and achieved large reduction of power consumption on the average.	en_US
dc.language.iso	en_US	en_US
dc.subject	low-power design	en_US
dc.subject	Reed-Soloman codes	en_US
dc.subject	two-stage syndrome calculator	en_US
dc.subject	Berlekamp-Massey algorithm	en_US
dc.subject	Euclidean algorithm	en_US
dc.title	A low-power design for Reed-Solomon decoders	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1142/S0218126603000726	en_US
dc.identifier.journal	JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS	en_US
dc.citation.volume	12	en_US
dc.citation.issue	2	en_US
dc.citation.spage	159	en_US
dc.citation.epage	170	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000184321400004	-
dc.citation.woscount	0	-
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