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dc.contributor.authorLin, Liang-Yuen_US
dc.contributor.authorLin, Huang-Kaien_US
dc.contributor.authorWang, Cheng-Yehen_US
dc.contributor.authorVan, Lan-Daen_US
dc.contributor.authorJou, Jing-Yangen_US
dc.date.accessioned2014-12-08T15:41:16Z-
dc.date.available2014-12-08T15:41:16Z-
dc.date.issued2009en_US
dc.identifier.isbn978-1-4244-2781-9en_US
dc.identifier.urihttp://hdl.handle.net/11536/28065-
dc.description.abstractIn this paper, we propose one hierarchical 2-D mesh Network-on-Chip (NoC) platform to support applications with the complexity of several hundreds of tasks or with huge amount of transmission data. Moreover, applying the task binding method by considering communication amount, communication data contention and bandwidth penalty to enhance the system overall performance of the new architecture. Modeling the NoC system data transmission behavior at system level is applied to predict system overall performance and an automatic NoC system performance simulation too] is also built. Therefore, architecture and designer.,; can predict the system performance and obtain all parameters of the designed platform at system abstraction level. The experimental results show that the overall system throughput, the latency, and the saving of redundant transactions are improved by 27%. 14.4% and 21.8% respectively under the communication dominated situation.en_US
dc.language.isoen_USen_US
dc.titleHierarchical Architecture for Network-on-Chip Platformen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAMen_US
dc.citation.spage343en_US
dc.citation.epage346en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000271941200086-
Appears in Collections:Conferences Paper