單晶片網路系統的階層式架構

Abstract

隨著半導體製程的進步，在未來十年後將有可能實現單一晶片上整合上百個運算元件。屆時，各元件之間的通訊將會是影響系統效能的一大關鍵。IC設計工程師需要一個能考慮通訊效能的系統設計方法。在這篇論文中，改良傳統二維網狀單晶片網路系統平台而提出階層式架構。此架構用以支援幾百個任務的複雜度或擁有大量資料傳輸的應用。此外，藉由考慮傳輸資料量、資料傳輸衝突和頻寬設限損失的任務結合方法來達到新架構的整體系統效能的提升。並在系統層級模擬單晶片網路系統的資料傳輸行為以預測整體系統效能。建立一自動化的單晶片網路系統效能模擬工具，IC設計工程師在系統層級得藉此工具預測所設計平台的效能且得到所設計平台的設計參數，補足自應用階段至RTL階段的設計斷層，以節省所需的設計時間和成本。

As the advance of semiconductor technology, it is possible to integrate hundreds of processing elements on a single chip in the next decade. When the time comes, communication between the components will be the critical factor for system performance. IC designers need a communication-driven system design methodology. In this thesis, improving the traditional 2-D mesh Network-on-Chip (NoC) platform by the hierarchical architecture is proposed. The hierarchical architecture is used to support applications with the complexity of several hundreds of tasks or with large amount of transmission data. Besides, applying the task binding method by considering communication amount, communication data contention and bandwidth penalty to achieve the system overall performance improvement of the new architecture. Modeling the NoC system data transmission behavior at system level is applied to predict system overall performance. Then, an automatic NoC system performance simulation tool is built. Therefore, IC designers can predict the system performance and get all parameters of designed platform at system level. That will make up the design gap between the application level and RTL level to reduce the design time and the design cost.