VLSI IMPLEMENTATION OF AN M-ARRAY IMAGE FILTER BASED ON SHIFT REGISTER ARRAY

Abstract

This paper presents a novel VLSI solution for sorting input samples in the transform domain to achieve real-time performance for image/video applications. The sorting is based on a dedicated memory containing so-called bar-chart information. The required value, such as median, can be generated from MSB to LSB sequentially by successively evaluating each bit of the memory content. In the architecture design, the dedicated memory is realized by (1) level control unit and (2) shift register arrays. To speed up the formation of bar-charts, the level control unit provides parallel control signals to the shift register arrays. Moreover, such an architecture can easily be updated when running any order operations are concerned. Our current design can handle at most 25 input samples with word-length of 8 bits, and the resultant IC shows that a 25-MHz clock rate can be achieved and the chip area is 0.69 x 0.56 cm2.